things required to enable interrupts on a blackfin processor, not necessarily in order though all are required (also see the list, in the programming ref, on page 4-31):
- set the ISR address in the EVTx (event vector) registers. (page 4-42 in the processor programming reference)
- set the system interrupt controller interrupt mask (SIC_IMASK) for the events you want to accept. for the blackfin BF537, see 4-20 in the hardware reference.
- set the interrupt priority with the IARx registers. This is also hardware-dependent, see page 4-18 in the BF537 hardware ref. BF537 has 4 of these registers, each 32 bits.
- remember to put the priority minus 7 in the individual nibbles of the IAR registers - hence '3' maps to IVG10
- set IMASK bits appropriately -- this is not the same as the SIC_IMASK register. See page 4-39 in the programming reference.
- if you want to allow nested interrupts, save reti, asat, and the fp (in addition to any registers clobbered) into the stack. If not, issue a cli and an sti before concluding the in the interrupt servicing routine.
- close your interrupt routines with a rti instruction.
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